Pushing the Speed Envelope for Memory System Designs
Time
November 28, 2023 | 10:00 AM CET
About
Memory interface speeds keep increasing to meet performance demand. For instance, DDR5 is 275% faster than DDR4, reaching 8800 MT/s or more. Higher speeds also complicate memory design and validation. To achieve the next memory standard, designers need a connected workflow that streamlines time-to-insight from concept to simulation and test.
In this webinar, you will learn from industry experts:
- Best practices pathfinding for complex modulation interfaces.
- Understand jitter amplification and equalization as speeds increase.
- Improve analysis accuracy using probe models to account for equipment loading effects.
Hee Soo Lee
SerDes Product Owner at Keysight Technologies
HeeSoo LEE is the SerDes/DDR product owner in the EEsof EDA group of Keysight Technologies DES division, located Santa Rosa California, USA. He has held several different positions in Keysight Technologies, Agilent Technologies, and Hewlett-Packard including consulting business manager, technical marketing lead, and field applications engineer since 1989. Before, he worked for Daeryung Ind. Inc. as a RF/MW circuit design engineer. He has over 30 years of design and simulation experience in the area of RF, microwave, and high-speed digital designs. He graduated with a BSEE degree from the Hankuk Aviation University, South Korea.
Additional Details
Preis -
Link zur Veranstaltungsseite - https://online-events.keysight.com/keysight-technologies7/Pushing-the-Speed-Envelope-for-Memory-System-Designs-emo?elq_cid=3480472&cmpid=ELQ-28339
